The present invention relates to the field of power converters, and in particular to a hysteretic converter wherein a feedback voltage is compared with a controlled ramp voltage added to a reference voltage.
Various schemes of controlling a DC to DC power converter are known. In a linear controlled power converter, one of the output voltage and output current are sensed and fedback to the controller via an error amplifier. A reference value, reflective of a target output, is further received by the error amplifier, and differences in output from the target output are detected and compensated for, typically by adjusting the amount of time that an electronically controlled switch is closed. In such an embodiment, the output voltage or current varies about the target output, and the average output over time may equal the target output. Such a linear regulation control however is inappropriate when a quick reaction to large changes in load is required.
In order to overcome this difficulty, a hysteretic converter is utilized. The hysteretic converter comprises at least one electronically controlled switch, a comparator and an inductor, the electronically controlled switch being closed responsive to the output of the comparator. The comparator is arranged to close the electronically controlled switch promptly responsive to the instantaneous output voltage falling below a first reference signal, thus driving the output voltage higher without the delay of an integrator or other low bandwidth circuitry. Various schemes for opening the electronically controlled switch exist, including, but not limited to, comparing the output voltage to a second reference and defining a predetermined fixed on time for the electronically controlled switch.
FIG. 1 illustrates a high level schematic diagram of a hysteretic converter 10 of the prior art comprising: a hysteretic comparator 20 illustrated as a Schmidt trigger comparator; a switched mode power supply 40, illustrated without limitation as a buck converter constituted of a first electronically controlled switch 50 illustrated without limitation as a p-channel field-effect transistor (PFET), a second electronically controlled switch 60 illustrated without limitation as an n-channel field-effect transistor (NFET), an inductor 70 and an output capacitor 80. Additionally, a load 90 is further illustrated. An input voltage VIN is connected to the source of PFET 50, and the drain of PFET 50 is connected to a first end of inductor 70 and to the drain of NFET 60. A second end of inductor 70 is connected to a first end of output capacitor 80 and to a first end of load 90, the voltage thereat denoted output voltage VOUT. A second end of load 90, a second end of output capacitor 80 and the source of NFET 60 are connected to a common potential.
Output voltage VOUT is further connected to the non-inverting input of hysteretic comparator 20 and a reference voltage VREF is connected to the inverting input of hysteretic comparator 20. The output of hysteretic comparator 20 is connected to both the gate of PFET 50 and to the gate of NFET 60. Optionally, (not shown) a gate driving circuit is provided between the output of hysteretic comparator 20 and the gates of PFET 50 and NFET 60. Output voltage VOUT is illustrated as being fed directly to the non-inverting input of hysteretic comparator 20, however this is not meant to be limiting in any way, and a function of output voltage VOUT, such as a voltage divided output consonant with reference voltage VREF, may alternately be fed back to the non-inverting input of hysteretic comparator 20, preferably any function being without active devices which result in a reduced bandwidth for response to changes in load 100.
In operation, when output voltage VOUT falls to less than the threshold value signal fed to the inverting input of hysteretic comparator 20, i.e. reference voltage VREF, hysteretic comparator 20 enables current flow through PFET 50, thus connecting inductor 70 to input voltage VIN and enabling increased current flow through inductor 70, defined as positive when flowing in the direction of output capacitor 80, thus increasing output voltage VOUT. When output voltage VOUT is greater than reference voltage VREF, hysteretic comparator 20 enables current flow through NFET 60, thus connecting inductor 70 to the common potential enabling current to freewheel through NFET 60; current flow through inductor 70 decreases over time thus decreasing output voltage VOUT. Hysteresis is provided by hysteretic comparator 20 to avoid instability.
Unfortunately, hysteretic converters typically exhibit unstable behavior in a circuit where the output capacitor exhibits a low equivalent series resistance, since the output voltage does not rise promptly responsive to the closing of the electronically controlled switch. Various resolutions to the above drawback have been proposed, primarily by artificially inducing a ripple which is in phase with the inductor current.
In one solution, as described in U.S. Pat. No. 6,791,306 issued Sep. 14, 2004 to Walters et al, the entire contents of which is incorporated herein by reference, a transconductance amplifier is provided connected across the inductor. The current generated by the transconductance amplifier is fed to a ripple voltage capacitor which transforms the current into an inductor current-representative voltage for input to the hysteretic comparator. Such a solution requires an input from both sides of the inductor, which may be difficult to accomplish.
In another solution, as described in U.S. Pat. No. 7,457,140 issued Nov. 25, 2008 to Klein, the entire contents of which is incorporated herein by reference, a ramp voltage, which is proportional to current flowing through the inductor, is generated and added to an output voltage representation, the summed voltage fed as an input to the hysteretic comparator. The embodiments shown are complex, requiring either the aforementioned input from both sides of the inductor, and/or dual edge one shot circuits.